View CAT24C128LI-GT3_8943931.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? catalyst semiconductor, inc. characteristics subject to change without notice doc. no. md-1103, rev. j cat24c128 128-kb i 2 c cmos serial eeprom pin configuration functional symbol features supports standard and fast i 2 c protocol 1.8v to 5.5v supply voltage range 64-byte page write buffer hardware write protection for entire memory schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda). low power cmos technology 1,000,000 program/erase cycles 100 year data retention industrial and extended temperature range rohs-compliant 8-lead pdip, soic, tssop and udfn packages pdip (l) soic (w) tssop (y) udfn (hu3) v cc v ss sd a scl wp cat24c128 a 2 , a 1 , a 0 device description the cat24c128 is a 128-kb serial cmos eeprom, internally organized as 16,384 words of 8 bits each. it features a 64-byte page write buffer and supports both the standard (100 khz) as well as fast (400 khz) i 2 c protocol. write operations can be inhibited by taking the wp pin high (this protects the entire memory). 8 7 6 5 v cc wp scl sda a 2 a 0 a 1 v ss 1 2 3 4 for the location of pin 1, please consult the corresponding package drawing. pin functions a 0 , a 1 , a 2 device address inputs sda serial data input/output scl serial clock input wp write protect input v cc power supply v ss ground * catalyst carries the i 2 c protocol under a license from the philips corporation. for additional packages and ordering information details, see page 15.
cat24c128 2 doc. no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice absolute maximum ratings (1) storage temperature -65c to +150c voltage on any pin with respect to ground (2) -0.5 v to +6.5 v reliability characteristics (3) symbol parameter min units n end (4) endurance 1,000,000 program/ erase cycles t dr data retention 100 years d.c. operating characteristics v cc = 1.8 v to 5.5 v, t a = -40c to +125c, unless otherwise speci?ed. symbol parameter test conditions min max units i ccr read current read, f scl = 400khz 1 ma i ccw write current write, f scl = 400khz 3 ma i sb standby current all i/o pins at gnd or v cc t a = -40c to +85c 1 a t a = -40c to +125c 2 i l i/o pin leakage pin at gnd or v cc t a = -40c to +85c 1 a t a = -40c to +125c 2 v il input low voltage -0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc < 2.5 v, i ol = 3.0ma 0.4 v v ol2 output low voltage v cc < 2.5 v, i ol = 1.0ma 0.2 v pin impedance characteristics v cc = 1.8 v to 5.5 v, t a = -40c to +125c, unless otherwise speci?ed. symbol parameter conditions max units c in (3) sda i/o pin capacitance v in = 0 v 8 pf c in (3) input capacitance (other pins) v in = 0 v 6 pf i wp (5) wp input current v in < v ih 200 a v in > v ih 1 a note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci - ?cation is not implied. exposure to any absolute maximum rating for extended periods may af fect device performance and reliability. (2) the dc input voltage on any pin should not be lower than -0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than -1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropriate aec-q100 and jedec test methods. (4) page mode, v cc = 5 v, 25c (5) when not driven, the wp pin is pulled down to gnd internally. for improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x vcc), the strong pull-down reverts to a weak current source.
cat24c128 3 doc no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice a.c. characteristics (1) v cc = 1.8 v to 5.5 v, t a = -40c to +125c. symbol parameter standard fast units min max min max f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 s t low low period of scl clock 4.7 1.3 s t high high period of scl clock 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data hold time 0 0 s t su:dat data setup time 250 100 ns t r sda and scl rise time 1000 300 ns t f (2) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t buf bus free time between stop and start 4.7 1.3 s t aa scl low to sda data out 3.5 0.9 s t dh data out hold time 100 100 ns t i (2) noise pulse filtered at scl and sda inputs 100 100 ns t su:wp wp setup time 0 0 s t hd:wp wp hold time 2.5 2.5 s t wr write cycle time 5 5 ms t pu (2, 3) power-up to ready mode 1 1 ms note: (1) test conditions according to a.c. test conditions table. (2) tested initially and after a design or process change that affects this paramete. (3) t pu is the delay between the time v cc is stable and the device is ready to accept commands. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.5 x v cc output load current source: i ol = 3 ma (v cc 2.5 v); i ol = 1 ma (v cc < 2.5 v); c l = 100 pf
cat24c128 4 doc. no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice power-on reset (por) the cat24c128 incorporates power-on reset (por) circuitry which protects the device against powering up in the wrong state. the cat24c128 will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi-directional por feature protects the device against brown-out failure following a temporary loss of power. pin description scl: the serial clock input pin accepts the serial clock generated by the master. sda: the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a 0 , a 1 and a 2 : the address pins accept the device address. when not driven, these pins are pulled low internally. wp: the write protect input pin inhibits all write opera - tions, when pulled high. when not driven, this pin is pulled low internally. functional description the cat24c128 supports the inter-integrated circuit (i 2 c) bus data transmission protocol, which de?nes a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data ?ow is controlled by a master device, which generates the serial clock and all start and stop conditions. the cat24c128 acts as a slave device. master and slave alternate as either transmitter or receiver. up to 8 devices may be connected to the bus as determined by the device ad - dress inputs a 0 , a 1 , and a 2 . i 2 c bus protocol the i 2 c bus consists of two wires, scl and sda. the two wires are connected to the v cc supply via pull-up resistors. master and slave devices connect to the 2- wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to transmit a 0 and releases it to transmit a 1. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, the sda line must remain stable while the scl line is high . an sda transition while scl is high will be interpreted as a start or stop condition (figure 1). the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a wake-up call to all receivers. absent a start, a slave will not respond to commands. the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8-bit serial slave address. the ?rst 4 bits of the slave address are set to 1010, for normal read/write opera - tions (figure 2). the next 3 bits, a 2 , a 1 and a 0 , select one of 8 possible slave devices and must match the state of the external address pins. the last bit, r/ w , speci?es whether a read (1) or write (0) operation is to be performed. acknowledge after processing the slave address, the slave responds with an acknowledge (ack) by pulling down the sda line during the 9 th clock cycle (figure 3). the slave will also acknowledge all address bytes and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9 th clock cycle. as long as the master acknowl - edges the data, the slave will continue transmitting. the master terminates the session by not acknowledging the last data byte (noack) and by issuing a stop condition. bus timing is illustrated in figure 4.
cat24c128 5 doc no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice figure 3. acknowledge timing figure 2. slave address bits 1 8 9 start scl from master bus release delay (transmitter) ack delay ( t aa ) ack setup ( t su:dat ) bus release delay (receiver) data output from transmitter data output from receiver start condition stop condition sda scl figure 1. start/stop conditions figure 4. bus timing t high scl sda in sda out t low t f t low t r t buf t su:s to t su:d at t hd:d at t hd:s ta t su:s ta t aa t dh 1 0 1 0 device address a 2 a 1 a 0 r/w
cat24c128 6 doc. no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice write operations byte write upon receiving a slave address with the r/ w bit set to 0, the cat24c128 will interpret the next two bytes as address bytes these bytes are used to initialize the internal address counter; the 2 most signi?cant bits are dont care, the next 8 point to one of 256 available pages and the last 6 point to a location within a 64 byte page. a byte following the address bytes will be interpreted as data. the data will be loaded into the page write buffer and will eventually be written to memory at the address speci?ed by the 14 active address bits provided earlier. the cat24c128 will acknowledge the slave address, address bytes and data byte. the master then starts the internal write cycle by issuing a stop condition (figure 5). during the internal write cycle (t wr ), the sda output will be tri-stated and additional read or write requests will be ignored (figure 6). page write by continuing to load data into the page write buffer after the 1 st data byte and before issuing the stop condition, up to 64 bytes can be written simultaneously during one internal write cycle (figure 7). if more data bytes are loaded than locations available to the end of page, then loading will continue from the beginning of page, i.e. the page address is latched and the address count automatically increments to and then wraps- around at the page boundary. previously loaded data can thus be overwritten by new data. what is eventually written to memory re?ects the latest page write buffer contents. only data loaded within the most recent page write sequence will be written to memory. acknowledge polling the ready/busy status of the cat24c128 can be ascer - tained by sending read or write requests immediately following the stop condition that initiated the internal write cycle. as long as internal write is in progress, the cat24c128 will not acknowledge the slave address. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left floating or is grounded, it has no im - pact on the operation of the cat24c128. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the ?rst data byte (figure 8). if the wp pin is high during the strobe in - terval, the cat24c128 will not acknowledge the data byte and the write request will be rejected. delivery state the cat24c128 is shipped erased, i.e., all bytes are ffh.
cat24c128 7 doc no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice sla ve address s a c k a c k a c k bus ac tivity : master slave s t a r t address byte a 13 Ca 8 address byte a 7 Ca 0 data byte n data byte n+1 data byte n+p a c k s t o p a c k a c k p a c k * * * = don't care bit p 63 t wr st op condition st ar t condition address ac k 8 th bit byte n scl sd a figure 5. byte write sequence sla ve address s a c k a c k a c k s t o p p bus ac tivity : master slave s t a r t address byte a 13 Ca 8 address byte a 7 Ca 0 data byte a c k * * * = don't care bit figure 7. page write sequence figure 6. write cycle timing figure 8. wp timing 1 8 9 1 8 a 7 a 0 d 7 d 0 t su:w p t hd:w p address byte data byte scl sda wp
cat24c128 8 doc. no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice read operations immediate read upon receiving a slave address with the r/ w bit set to 1, the cat24c128 will interpret this as a request for data residing at the current byte address in memory. the cat24c128 will acknowledge the slave address, will immediately shift out the data residing at the current address, and will then wait for the master to respond. if the master does not acknowledge the data (noack) and then follows up with a stop condition (figure 9), the cat24c128 returns to standby mode. selective read to read data residing at a speci?c location, the internal address counter must ?rst be initialized as described under byte write. if rather than following up the two address bytes with data, the master instead follows up with an immediate read sequence, then the cat24c128 will use the 14 active addres bits to initialize the inter - nal address counter and will shift out data residing at the corresponding location. if the master does not ac - knowledge the data (noack) and then follows up with a stop condition (figure 10), the cat24c128 returns to standby mode. sequential read if during a read session the master acknowledges the 1 st data byte, then the cat24c128 will continue trans - mitting data residing at subsequent locations until the master responds with a noack, followed by a stop (figure 11). in contrast to page write, during sequential read the address count will automatically increment to and then wrap-around at end of memory (rather than end of page).
cat24c128 9 doc no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice figure 11. sequential read sequence bus ac tivity : master slave data byte n data byte n+1 data byte n+2 data byte n+x a c k a c k a c k s t o p n o a c k a c k p sla ve address figure 10. selective read sequence sla ve address s a c k a c k a c k bus ac tivity : master slave s t a r t address byte a 13 Ca 8 address byte a 7 Ca 0 data byte sla ve address s a c k n o a c k s t a r t p s t o p * * * = don't care bit figure 9. immediate read sequence and timing scl sd a 8 th bit st op no ac k da ta out 8 9 sla ve address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave
cat24c128 10 doc. no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice package outline drawing e1 d a l e b b2 a1 a2 e eb c to p view side view end view pin # 1 identifica tion pa ckage outline dra wing pdip 8-lead 300mils (l) doc. no. pdip8-001-01 06/26/07 notes: (1) all dimensions are in millimeters. (2) complies with jedec ms-001. symbol min nom max a 5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.25 e 2.54 bsc e1 6.10 6.35 7. 11 eb 7.87 10.92 l 2.92 3.30 3.80 notes: 1. all dimensions are in millimeters. 2. complies with jedec ms-001. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf. pdip 8-lead 300mils (l)
cat24c128 11 doc no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice soic 8-lead 150mils (w) e1 e a a1 h l c e b d pin # 1 identifica tion to p view side view end view pa ckage informa tion soic 8-lead 150 mils (v , w) doc. no. soic8-002-01 07/24/2007 notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. a 1 .35 1 .7 5 a1 0.10 0.25 b 0.33 0 .5 1 c 0.19 0 .2 5 d 4.80 5 .0 0 e 5.80 6 .2 0 e1 3.80 4.00 e 1.27 bsc h 0.25 0 .5 0 l 0.40 1 .2 7 0o 8 o symbol min nom max notes: 1. all dimensions are in millimeters. 2. complies with jedec ms-012. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat24c128 12 doc. no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice tssop 8-l ead 4.4mm (y) a2 e1 e a1 e b d c a to p view side view end view 1 l1 l doc. no. tssop8-004-01 06/21/07 symbol min nom max a 1 .2 0 a 1 0.05 0.15 a 2 0.80 0.90 1.05 b 0.19 0 .3 0 c 0.09 0 .2 0 d 2.90 3.00 3.10 e 6.30 6.40 6.50 e 1 4.30 4.40 4.50 e 0.65 bsc l 1.00 re f l 1 0.50 0.60 0.75 1 0 8 notes: 1. all dimensions are in millimeters. angles in degrees. 2. complies with jedec mo-153. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat24c128 13 doc no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice udfn 8-pad 2 x 3mm (hu3) e2 d2 k l e pin #1 index area pin #1 identifica tion dap size 1.3 x 1.8 det ail a d a1 b e a to p view side view front view det ail a bott om view a3 a a1 pa ckage outline dra win g udfn 8-pad 2 x 3mm (hu3) doc. no. udfn8-032-02 08/29/07 notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-229. symbol min nom max a 0.45 0.50 0.55 a1 0.00 0.02 0.05 a3 0.127 ref b 0.20 0.25 0.30 d 1.90 2.00 2.10 d2 1.50 1.60 1.70 e 2.90 3.00 3.10 e2 0.10 0.20 0.30 e 0.50 ty p k 0.10 ref l 0.30 0.35 0.40 notes: 1. all dimensions are in millimeters. 2. complies with jedec mo-229. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat24c128 14 doc. no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice msop 8-l ead 3.0 x 3.0mm (z) e1 e a2 a1 e b d c a to p view side view end view l1 l2 l det ail a det ail a doc. no. msop8-003-01 07/18/07 pa ckage outline dra win g msop 8-lead 3.0 x 3.0mm (r, z) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-187. symbol min nom max a 1 .1 0 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.22 0 .3 8 c 0.13 0 .2 3 d 2.90 3.00 3.10 e 4.80 4.90 5.00 e 1 2.90 3.00 3.10 e 0.65 bsc l 0.40 0.60 0.80 l 1 0.95 ref l 2 0.25 bsc 0o 6 o notes: 1. all dimensions are in millimeters. angles in degrees. 2. complies with jedec mo-187. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat24c128 15 doc no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice ordering information notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard lead ?nish is nipdau. (3) the device used in the above example is a cat24c128yi-gt3 (tssop, industrial temperature, nipdau, tape & reel). (4) for additional package and temperature options, please contact your nearest catalyst semiconductor sales of?ce. prefix device # suffix 24c128 y i t3 product number 24c128 C g cat temperature range i = industrial (-40 c to +85 c) e = extended (-40 c to +125 c) company id t: tape & reel 3: 3000/reel lead finish g: nipdau blank: matte-tin package l: pdip w: soic, jedec y: tssop hu3: udfn (2 x 3mm) z: msop
cat24c128 16 doc. no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice revision history date revision comments 10/07/05 a initial issue 11/16/05 b update ordering information add tape and reel speci?cations 02/02/06 c update a.c. characteristics update ordering information 03/13/06 d update a.c. characteristics 04/26/06 e update features update device description update pin con?guration update a.c. characteristics update hardware write protecttion add figure 6a add 8-lead tssop package drawing update ordering information add 8-lead tssop package marking 05/19/06 f update features update device description update pin con?guration update ordering information update d.c. operating characteristics update pin impedance characteristics update a.c. characteristics add power-on reset (por) update 8-lead pdip package drawing update 8-lead soic package drawing update 8-lead tssop package drawing update tape and reel 08/11/06 g update features update d.c. operating characteristics update pin impedance characteristics update a.c. test conditions update power-on reset (por) update pin description update i 2 c bus protocol update device addressing update acknowledge update write operations update byte write update page write update acknowledge polling add delivery state update read operations update selective read update sequential read update figure 1, 2, 3, 5, 6, 6a, 7, 8, 9 and 10 update part marking update ordering information 08/21/07 h add extended temperature range update d.c. operating characteristics table update package outline drawings and add udfn package outline drawing add md- to document number 08/29/07 i update udfn package outline drawing to include e dimension. 09/18/07 j add msop package outline drawing
cat24c128 17 doc no. md-1103, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice copyrights, trademarks and patents ? catalyst semiconductor, inc. trademarks and registered trademarks of catalyst semiconductor include each of the following: beyond memory ?, dpp ?, ezdim ?, ldd ?, minipot? and quad-mode? catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability arising out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. products with data sheets labeled advance information or preliminary and other products described herein may not be in production or offered for sale. catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing orders. cir cuit diagrams illustrate typical semiconductor applications and may not be complete.
catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: md-1103 revison: j issue date: 09/18/07

▲Up To Search▲

Price & Availability of CAT24C128LI-GT3

	To Download CAT24C128LI-GT3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .